VLSI Design -- Summer 1998

Laboratory Exercise 1

Due June 22, 1998

FAQ

 Important - summer additions to the FAQ.

Q1: How do I attach a input or output signal port (Metal 2) to a Metal 1 line? Is there an interconnect?
Ans - Metal1 is connected to metal2 using vias (add shape-via)

Q2: To connect a metal line to the FET, I just lay a metal 1 over the point
I want to connect to, then add a "poly-connect" square between metal 1 and
the FET right?
Ans - To connect metal1 to a poly you need to use a contact-to-poly. Also after
you have put down the contact, add a 5x5 Lambda shape of metal1 and poly
around the contact.

Q3: Why do we need to place diffusion contacts? What are they for?
Ans - They are channel stops to prevent 1 FETs diffusion layer from interacting
with the next FET.

Q4: Step 21a says to connect the n-well's contact port with the VDD port,
and p-well's contact port to the VSS. Is this right or is this backwards?
Ans - It is right, the wells have to be reverse biased.

How can I run Mentor Graphics from a workstation that is not in the LRC ?
Assuming that the workstation is a Unix workststion and is running X. Rlogin to the LRC m/c's , Set the display.
You would also need to set the font path with:
xset +fp tcp/128.83.59.201:7000
My colors on the Mentor Graphics tools do not appear correct. Why?
This might happen if you have invoked Netscape before you invoked Mentor Graphics. The way to get around this is to always invoke netscape with
netscape -install &
Where can I access the design rules for this exercise ?
Check out the URL
http://www.mosis.org/scmos72.html In your case you are using the 2.0 micron process. Thus lambda shall be 1. You may als look up the rules in the centre flap of your textbook.
I saved my IC session and now it does not allow me to edit it any more?
When you save a session IC gets out of the edit mode. Get it back into the edit mode by hitting CNTRL-m
How do I get online help?
Invoke the online docs. by saying
mentor-docs
I messed up my design., How do I delete it and start over?
You need to invoke design manager with dmgr and drag the design to the trash can. See the online help for details.
I'm having problems while placing ports. I do not get all four ports on invoking the mports command. Moreover sometimes I get one large port which has an area of 1000 or something bizzare of the same sort?
This problem would occur if you have (accidentally ) altered connectivity of the circuit. To avoid such problems I suggest the following altered procedure.
Place the ports as soon as you have placed the cells. You should get all four ports and should also get the overflow lines indicating connectivity. Now continue as described in the original procedure.
If you have had the port problem already, you might want to start on the layout part afresh. However first you would mneed to junk your old design.Do this as follows:

1. Invoke design manager with "dmgr"

2. Navigate to the "Class" directory and locate the inverter layout icon. It should have a small picture of a layout on it. Click on it and drag it to the trash bin.

3. Now start again with a different name than the one you had before i.e. if your layout was called "inverter" earlier - call it "inv" now.

4. You have to set the logic in IC as usual.
A graceful way to quit Mentor_tools .... < courtesy Indumati Madhavan
Someone finally discovered a neat way to quit the Mentor tools without being brutal and using the delete button. Press "Shift-F12" in the Mentor Graphics window. You shall be prompted to choose between quit with save or without save option
Overlapping ports in DA. If you get a cryptic error message that reads something like - I$23 overlapps I$12..... < courtesy Jay Yang >
DA assumes an invisible bounding box around each of the components . When the components are placed very close to each other these bounding boxes may overlap. Moving the components away from each other helps.
Use "select->by Handle" and type "I$whatever" to see the referred component highlighted. This holds for ic station too.
When placing ports the GND/VSS port does not have an Overflow
That is ok. Just add the overflow and place the port on top of the VSS line.
Do I choose "Metal1.port" or "Metal1" when changing port metal layers?
Metal1.port